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  1. Aug 2022
  2. www.intel.com www.intel.com
    Post-barrier Return Stack Buffer Predictions
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    1. terminus 11 Aug 2022
      IBPB command event, or (on processors which support enhanced IBRS) either a VM exit with IBRS set to 1 or setting IBRS to 1 after a VM exit.

      So either a barrier via IBPB or IBRS=any?

      after case: the IBRS, presumably walks and cleans up context specific state? already set: checks for it on control change?

      spectre ibrs ibpb
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    intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/advisory-guidance/post-barrier-return-stack-buffer-predictions.html