variable latency while accessing contiguous across slices could be backed up by spatial prefetcher.

n-way set associativity.

Especially is prefetching triggers reads from a remote node.

For latency sensitive workloads with high remote memory accesses.

Power saving from downgrading QPI bandwidth can provide extra head room for core scaling, but increase data access latency by cpus

through PCU

primitive object

Increase in code size may also have effect on the ITLB misses, this is because the static object size will now fit in more number of pages and hence code size expansion optimizations may also cause ITLB misses which stores a portion of page table (virtaul-physical mappings)

Binding specific physical address spaces to a memory controller along with constraining all the memory request from given set of CPU cores to be directed to particular memory controller makes sure that on a cache miss the memory access request goes to the HOME agent of that specific memory controller, this offers a low latency path and is the core concept behind numa.

this together with multi-port memory can facilitate concurrent non conflicting memory access since each memory controller can only access specific memory banks (address space).

Native interface

Mini batch size of 1 : Stochastic gradient descent.