14 Matching Annotations
- Last 7 days
-
www.intel.com www.intel.com
-
Being at maximum temperature while running a workload isn't necessarily cause for concern. Intel processors constantly monitor their temperature and can very rapidly adjust their frequency and power consumption to prevent overheating and damage.
Intel says there is no need to worry about CPU run at maximum temperature.
-
- Apr 2023
-
yosefk.com yosefk.com
-
Very nice article explaining the HW performance of GPUs, from 2011.
-
- Dec 2022
-
www.zhihu.com www.zhihu.com
-
CEK machine里的C、E、K分别对应了“真实”计算机里的哪些构造?
Tags
Annotators
URL
-
-
www.zhihu.com www.zhihu.com
-
如何通俗的解释计算机是如何实现1+1=2计算的?
-
- Aug 2022
-
-
只有在真正的多核CPU上才可能得到加速(通过多线程)
CPU
Tags
Annotators
URL
-
-
www.zhihu.com www.zhihu.com
-
API网关、防火墙、路由器等流量入口的服务器,要对流量做密集计算、校验、转发,CPU不强那肯定是不行的
Tags
Annotators
URL
-
- May 2021
-
github.com github.com
-
Disclaimer If this tool works, great! However, no guarantees are made that it won't hasten the heat death of the universe through the spontaneous combustion of your CPU.
-
- Dec 2020
-
en.wikipedia.org en.wikipedia.org
-
Real mode is characterized by a 20-bit segmented memory address space (giving exactly 1 MiB of addressable memory) and unlimited direct software access to all addressable memory, I/O addresses and peripheral hardware
-
- Mar 2019
- Nov 2018
- Mar 2018
-
Local file Local file
-
short-term scheduler
也称为CPU调度程序, 完成的功能就是从内存中选择一个 ready 状态的进程开始执行, 并将CPU分配给该进程.
-
- May 2017
-
stackoverflow.com stackoverflow.com
-
Optimum buffer size is related to a number of things: file system block size, CPU cache size and cache latency. Most file systems are configured to use block sizes of 4096 or 8192. In theory, if you configure your buffer size so you are reading a few bytes more than the disk block, the operations with the file system can be extremely inefficient (i.e. if you configured your buffer to read 4100 bytes at a time, each read would require 2 block reads by the file system). If the blocks are already in cache, then you wind up paying the price of RAM -> L3/L2 cache latency. If you are unlucky and the blocks are not in cache yet, the you pay the price of the disk->RAM latency as well. This is why you see most buffers sized as a power of 2, and generally larger than (or equal to) the disk block size. This means that one of your stream reads could result in multiple disk block reads - but those reads will always use a full block - no wasted reads. Now, this is offset quite a bit in a typical streaming scenario because the block that is read from disk is going to still be in memory when you hit the next read (we are doing sequential reads here, after all) - so you wind up paying the RAM -> L3/L2 cache latency price on the next read, but not the disk->RAM latency. In terms of order of magnitude, disk->RAM latency is so slow that it pretty much swamps any other latency you might be dealing with. So, I suspect that if you ran a test with different cache sizes (haven't done this myself), you will probably find a big impact of cache size up to the size of the file system block. Above that, I suspect that things would level out pretty quickly. There are a ton of conditions and exceptions here - the complexities of the system are actually quite staggering (just getting a handle on L3 -> L2 cache transfers is mind bogglingly complex, and it changes with every CPU type). This leads to the 'real world' answer: If your app is like 99% out there, set the cache size to 8192 and move on (even better, choose encapsulation over performance and use BufferedInputStream to hide the details). If you are in the 1% of apps that are highly dependent on disk throughput, craft your implementation so you can swap out different disk interaction strategies, and provide the knobs and dials to allow your users to test and optimize (or come up with some self optimizing system).
What's the cache size to keep when reading from file to a buffer?
-
- Jan 2016
-
twitter.com twitter.com
-
Computer hardware is also full of bugs.
-
- Mar 2015
-
-
RISC-V: free and open instruction set architecture (ISA). including "rocket chip" cpu reference implementation.
Tags
Annotators
URL
-